Programmable logic devices (PLDs) are a well-known type of digital integrated circuit that can be programmed to perform specified logic functions. For example, one type of PLD, the field programmable gate array (FPGA), typically includes an array of configurable logic blocks (CLBs) surrounded by a ring of programmable input/output blocks (IOBs). Some FPGAs also include additional logic blocks with special purposes (e.g., DLLs, RAMs, processors, and so forth).
FPGA logic blocks typically include programmable logic elements such as lookup tables (LUTs), memory elements, multiplexers, and so forth. The LUTs are typically implemented as RAM arrays in which values are stored during “configuration” (i.e., programming) of the FPGA. The flip-flops, multiplexers, and other components are also programmed by writing configuration data to configuration memory cells included in the logic block. For example, the configuration data bits can enable or disable elements, alter the aspect ratios of memory arrays, select latch or flip-flop functionality for a memory element, and so forth. The configuration data bits can also interconnect the logic elements in various ways within a logic block by programming select values for multiplexers inserted in the interconnect paths within the logic block.
The various logic blocks are interconnected by a programmable interconnect structure that includes a large number of programmable interconnect lines (e.g., metal traces). The interconnect lines and logic blocks are interconnected using programmable interconnect points (PIPs). For example, a PIP can be implemented as a simple CMOS passgate. When the passgate is turned on, the two interconnect lines on either side of the passgate are electrically connected. When the passgate is turned off, the two interconnect lines are isolated from each other. Thus, by controlling the values on the gate terminals of the passgates, circuit connections can be easily made and altered. The value controlling each passgate is also stored in a configuration memory cell.
FIG. 1 shows an exemplary implementation of a routing path between a source logic block (LB) 101 and a destination logic block 102. In the PLD of FIG. 1, each interconnect line (103-107) is driven by an associated programmable routing multiplexer (113-117, respectively). In some PLDs, interconnect line 103 is driven by a driver or multiplexer included in source logic block 101, i.e., multiplexer 113 is omitted. The path between the source 101 and destination 102 logic blocks traverses multiplexer 113, interconnect line 103, multiplexer 114, interconnect line 104, multiplexer 115, interconnect line 105, multiplexer 116, interconnect line 106, multiplexer 117, and interconnect line 107.
FIG. 2 shows one possible implementation of routing multiplexer 116 of FIG. 1, in which routing multiplexer 116 includes a 4-input multiplexer 201 controlled by two configuration memory cells MC1 and MC0. The values stored in configuration memory cells MC1 and MC0 select one of the input signals IN0-IN3 to be passed to the output node OUT. (In the present specification, the same reference characters are used to refer to terminals, interconnect lines, nodes, and their corresponding signals.) In the pictured example, input terminal IN1 of multiplexer 201 is coupled to interconnect line 105 of FIG. 1. The other input terminals IN0, IN2, IN3 are coupled to other interconnect lines (not shown). Configuration memory cells MC1 and MC0 store low and high values, respectively, selecting the signal on interconnect line 105 to be passed to the output node OUT through input terminal IN1. The output node OUT is coupled to interconnect line 106 of FIG. 1.
Routing multiplexers typically include more than four input signals, but four input signals are shown in FIG. 2, for clarity. The number of configuration memory cells controlling the multiplexer depends at least in part on the number of input signals to the multiplexer.
In FPGAs, configuration memory cells are typically implemented as static RAM (random access memory) cells. Each FPGA typically contains many thousands or even millions of these static RAM configuration memory cells.
When bombarded by high-energy particles, a static RAM cell can change state. For example, a stored high value can be inadvertently changed to a low value, and vice versa. These inadvertent and undesired state changes are known as “single event upsets”, or SEUs. Sometimes an SEU has no effect on the functionality of the design. At other times, an SEU can change the function of an FPGA such that the circuit implemented in the FPGA no longer functions properly.
For example, if a static RAM cell controlling a passgate changes state, but the two interconnect lines on either side of the passgate are not used in the design, this change of state has no effect on the function of the circuit. Similarly, a change of state in a memory cell in an unused LUT has no effect. However, when SEUs occur in portions of the FPGA that are in use, the SEUs can result in loss of function for the design implemented in the FPGA.
In some applications, such as space-based applications in a low-earth orbit, it is important to minimize the effects of SEUs in PLD-based (e.g., FPGA-based) designs. SEUs can also be a concern in some earth-based systems, e.g., systems in high altitude locations. One method of mitigating and minimizing these effects is “triple modular redundancy”, or TMR, in which three copies of a circuit are included in a design. Any two copies of the circuit can override output from the third copy, if it generates data different from the other copies. While useful in many applications, implementing a circuit using TMR requires about three times as many programmable resources as a standard implementation.
Therefore, it is desirable to provide methods other than TMR that will reduce the susceptibility to SEUs of a PLD design.